In recent years, techniques concerning a control method for plural instructions that cannot be executed simultaneously have been variously proposed for a processor which decodes the plural instructions and executes the decoded plural instructions in parallel.
As an example, a control mechanism in which instructions are sent to an execution stage, it is judged whether or not unusable data is depended during processing of the instructions at the execution stage, and only such instruction is suspended and other instructions are executed simultaneously in the case where it is judged to be depended on an instruction is provided. That is, a technique in which the processing is suspended by generating a hazard in the case where the instructions cannot be executed simultaneously after reaching the execution stage is proposed (for example, see Patent Reference 1).
Furthermore, it is judged whether the instructions can be executed simultaneously based on the number of unissued instructions in an instruction buffer and instruction registers corresponding to functional units, and an update control of registers is performed. In other words, a technique in which a circuit for monitoring an execution state is provided to a processor and the processing is suspended by controlling instruction supply before moving to the execution stage on the basis of information about what kind of the execution state an instruction preexisting in the functional unit is in is proposed (for example, see Patent Reference 2).
Patent Reference 1: Japanese Patent Application Laid-Open Publication No. 8-221273
Patent Reference 2: Japanese Patent Application Laid-Open Publication No. 8-305567